1. Field of the Invention
The present invention relates generally to testing of an electric workpiece including at least one electrical circuit provided on a substrate, printed circuit board, multi-chip module, and the like, and, particularly, to a system and method employing a thermal stimulus to a circuit for efficiently and accurately locating a defect, e.g., a short circuit or an incipient open circuit, which can be practiced in the absence of a priori knowledge of circuit geometry, and which uses electrical access only at circuit terminals.
2. Discussion of the Prior Art
It is often required to fabricate an electric workpiece including one or more electrical circuits, composed of suitable electrically conducting material conduits to carry either power or signal to and from various locations in electrical circuit structures.
These circuits may be either in the same plane, or may be in various planes stacked one over the other. Suitable electrical insulator materials separate these planes, in addition to separating the electrical conduits within a network. Electrical connections among conducting circuits in various planes are made through "vias" which perpendicularly connect plural planes. Some examples of an electric workpiece are: a printed circuit board, an electronic substrate, a multi-chip module, a flexible printed circuit sheet, etc.
During fabrication of an electric workpiece, it is possible that unwanted short circuit connections may inadvertently result, such as a short circuit or an incipient open circuit. These circuit defects may have a wide range of electrical resistance. Often, these defects must be located precisely for evaluation, analysis and possible repair. Incipient defects are unstable structures which may become either a short circuit or an open circuit condition at some time in the future. Incipient open circuits caused by a narrow neck in a circuit line, or chemical contamination. These defects may be detected by harmonic response analysis means disclosed by DiStefano, et al. in U.S. Pat. Nos. 4,496,900 and 4,868,506. Latent open defect detection is also described by Halperin, DiStefano and Chiang in "Latent Open Defect Detection Using Phase-Sensitive Nonlinearity Detection Technique", IEEE Transactions on Components, Packaging and Manufacturing, Part B, Vol. 18, No. 2, May 1995, pp. 358. As described in this reference, a circuit is driven with a modulated current, and a circuit defect is detected with electric non-linearity. For example, in a circuit driven with current at two frequencies Fdrive1 and Fdrive2, the circuit defect generated heterodyne modulation at a frequency: EQU Fdefect=Fdrive1+Fdrive2
In another example, there is a large current at Fdrive2=0 and the defect generated a homodyne modulation: EQU Fdefect=2 * Fdrive1
There are several prior techniques to locate a short circuit defect including (1) human visual inspection or robotic pattern recognition. Other techniques apply a sufficient alternating current (AC) through two circuits connected by an inadvertent short, thus, generating a local magnetic field at the point where the short circuit occurs. This short circuit may be located by a technique (2) which requires scanning with a small non-contacting loop and measuring the induced Electromagnetic Field (emf). In another prior art technique (3), a thin film of a material having a suitably high magnetic susceptibility is applied to the workpiece. Adjacent to the short circuit, the magnetic field induces optical birefringence in the magnetic material. Under optical inspection with polarized light, the location of the defect may be determined. In yet another prior art technique (4), an AC current is applied to a small loop of wire. When the loop is near the short, the AC magnetic field induces a current to flow between two shorted circuits, thus indicating the proximity to the location of the defect.
The problem with method (1) is fatigue and unreliability, if human inspection is used; unreliable pattern recognition due to topography and transparent insulating films if robotic inspection is used.
Methods (2) (3) (4) are essentially spot scanning methods and require a long search time to locate a defect which might be anywhere in a search region. Inconveniently, long search times occur in several important cases: for short circuits between power planes, for defects involving one or more wires whose path geometry is effectively not known, or for complex printed circuit boards. To locate a defect in three dimensions, such as in a printed circuit with many layers, becomes even more difficult.
By contrast, if a defect is somewhere along a known path, which is topologically one-dimensional, and if it is practical to search narrowly along this path, then it is much less difficult to locate the defect. However, this favorable situation often does not occur for shorts, and does not occur for a workpiece without a detailed circuit map.
A further problem with methods (2), (3) and (4) is loss of reliability when the shorting resistance is greater than 1 kOhms.
A further problem with methods (2), (3) and (4) is false positives which indicate the presence of a circuit shorting defect where there is none. These false positives originate from certain circuit features such as input and output connections, inter-plane connections and depend on circuit design.
A recurring problem for electronic printed circuit board (PCB) and multi-chip module (MCM) substrate fabrication is the inability to locate efficiently and accurately short defects or incipient open defects. The ability to effectively locate defects in complex network of electrical conductors has important consequences; once a defect is located and carefully analyzed, the resulting information often helps to improve manufacturing technique and manufacturing yield.
To locate a defect is very different than to detect the same defect. These defects often are simple to detect, using just an ohmmeter. However, a short circuit defect between two power planes may occur almost anywhere on the workpiece region where the two power planes come near each other, so such a defect is often very challenging to locate. Alternatives such as automated optical inspection (AOI) may have some level of effectiveness. Unfortunately, however, AOI often is very time consuming, and often misses some defects. Therefore, other techniques are often necessary.
A first prior art technique for locating a short circuit is a voltage gradient technique, such as described in the reference "Quick Inspection of Power Plane Short Fault on Multilayer Substrates," IEEE Transactions Comp. Packaging and Manufacturing Technology, USA, Vol. 18, No.3, September 1995, pp. 466-470 by Fang Lin Chao et al. This technique requires mechanical probe contact with the top surface metallurgy (TSM) and may be neither practical nor desirable. Non-contact methods of probing the surface are much more desirable.
A second technique utilizes magnetic induction, such as shown and described in co-pending U.S. patent application Ser. No. 08/807,076 [Atty. Docket # FI996163] entitled "METHOD AND APPARATUS FOR DETECTING SHORTS IN A MULTI-LAYER ELECTRONIC PACKAGE," commonly-owned by the assignee of the present invention. In particular, Faraday induction techniques which typically use an AC pickup coil, are described in commonly-owned, co-pending U.S. patent application Ser. No. 09/116,396 [Atty. Docket # FI998018] entitled "METHOD FOR DETECTING POWER PLANE-TO-POWER PLANE SHORTS AND I/O NET-TO-POWER PLANE SHORTS IN MODULES AND PRINTED CIRCUIT BOARDS." Faraday induction is often used effectively for low resistance shorts. However, Faraday induction is much less effective for high resistance shorts, particularly in the presence of significant capacitive coupling between power planes.
A third technique involves covering the printed circuit board surface with iron garnet, or another magneto-optical material, and inspecting this material with polarized light. A local magnetic field changes the polarization of reflected light. This method is shown and described in commonly-owned, co-pending U.S. patent application Ser. No. 09/139,515 [Atty. Docket # FI998012] entitled "METHOD AND APPARATUS FOR LOCATING POWER PLANE SHORTS USING POLARIZED LIGHT MICROSCOPY." Although this method has been used effectively, unfortunately, it tends to require fairly high current through the shorts to produce sufficiently high magnetic fields to image the defect using polarization techniques.
A fourth technique implements infrared optical emission such as described in the reference "Infrared Scanning for Hot Spots Increases Power Efficiency in producing High Purity Copper Sheet," Industrial Heating, v. 60, Dec. 12, 1993, p. 39 to Jackson Jenkins et al.. Infrared optical emission has often been used to find power plane shorts but it requires the defect to be fairly low resistance in order to generate sufficient heat. This technique is thus marginal to detect high resistance defects.
A fifth technique uses laser scanning for locating shorts, e.g., using the Seebeck effect, such as shown and described in "Backside Localization of Open and Shorted IC Interconnections," IEEE International Reliability Physics Symposium, 1998, pp. 129-36, March-April 1998 to E. I. Cole Jr. et al.
Alternately, in a sixth technique, the short circuit may be blown using a current stress technique, e.g., blowing high resistance sorts with a low current/high voltage spike or blowing low resistance shorts with a high current/low voltage DC. However, this may be excessively destructive and may not help to locate the defect for diagnostics.
Of the prior art techniques described above, the first is applicable to high resistance shorts, but is undesirable because it requires probing along a conducting line and is thus slow, limited to the top surface and may be regarded as destructive in some applications. The second, third and fourth techniques are applicable only to low resistance shorts of less than 1 kOhm. The fifth technique, while based on general physical principles, is most suitably applied to test sites in semiconductors as it relies on the Seebek effect to vary the bias conditions of an integrated transistor that forms part of its detection method. The sixth prior art technique is destructive and can only be applied once for each short circuit defect.
The first and fifth prior art techniques further require knowledge of the circuit path and geometry. While the second and third techniques do not require knowledge of circuit path geometry, these are rather slow spot scan methods, and further, are applicable only for defect shorts having a resistance of less than 1 kOhm. The fourth technique does not require knowledge of circuit line geometry, but, as discussed above, is also applicable for only for defect shorts having a resistance of less than 1 kOhm. The sixth technique does not require knowledge of circuit line geometry and is applicable to low and high resistance short circuit defects. Unfortunately, the sixth technique typically destroys the defect and its immediate neighborhood, which largely prevents further detailed analysis.
It would be highly desirable to provide a non-destructive means of rapidly locating unwanted resistive connections between a plurality of electrically isolated conductors and a power plane, or between two isolated electrical circuits or between two power planes, without prior knowledge of circuit lines geometry.